Caches used to access main memory in a computer system can be organized into discrete, hierarchical levels. Typically, each level obeys inclusion, replicating the contents of a smaller level above it, so as to reduce the number of accesses to lower levels of the hierarchy. As memory access bandwidth demands grow, and technology feature size is further reduced, the size of on-chip cache memories is expected to increase.
Single levels of cache have traditionally had uniform access times. This Uniform Cache Architecture (UCA) may be divided into multiple sub-banks to reduce access time. A central pre-decoder is often used to drive signals to local decoders in the sub-banks. Data can be accessed at each sub-bank and returned to the output drivers after passing through multiplexers, where the requested line is assembled and driven to the cache controller. Increasing the size of the cache may increase data access time, due in part to global wire delays across the cache. Such delays may then contribute to the bulk of data access time, due to routing time to and from the banks. Thus, even when an optimal sub-banking organization is used, large caches of this type may perform poorly because the wire-delay-dominated process holds up receiving a portion of a line from the slowest of the sub-banks.
Another problem which may arise is that of contention, including bank contention, which occurs when a request stalls because the needed bank is busy servicing a different request, and channel contention, which occurs when the bank is free but the routing path to the bank is busy. In a UCA cache, latencies due to port contention may be sufficiently high to cause substantial losses. Multiported cells can be a poor solution for overlapping accesses in large caches, since area increases may expand loaded access times significantly. This is why, in some cases, a dual-port cache may not perform as well as a single-ported solution.
Thus, there is a need for apparatus, systems, articles, and methods for more efficiently utilizing cache memory banks that are independently accessible. There is also a need for apparatus, systems, articles, and methods which operate to reduce contention in the cache environment.